1 Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems

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Hardware Trojan Threats to Cache Coherence in

Modern 2.5D Chiplet Systems

Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, and Paul V. Gratz

Abstract—As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a signiﬁcant threat to the security

of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive

target. Critically, unlike prior work, which focuses only on malicious packet modiﬁcations, a Trojan attack that exploits coherence can

modify data in memory that was never touched and is not owned by the chiplet which contains the Trojan. Further, the Trojan need not

even be physically between the victim and the memory controller to attack the victim’s memory transactions. Here, we explore the

fundamental attack vectors possible in chiplet-based systems and provide an example Trojan implementation capable of directly

modifying victim data in memory. This work aims to highlight the need for developing mechanisms that can protect and secure the

coherence scheme from these forms of attacks.

1 INTRODUCTION

COMPUTING systems are moving toward 2.5D designs

that source various hard IPs, called chiplets, from mul-

tiple vendors and integrate them using an interposer. In-

dustry has demonstrated that 2.5D designs lower manufac-

turing costs, enabling further scaling post-Moore’s Law [1].

Future 2.5D designs may leverage standards such as Com-

pute Express Link [2] to interoperate via a shared memory

system. While 2.5D designs provide many beneﬁts, we show

they also increase the risk of Trojan attacks, speciﬁcally tar-

geting the coherence system. Here, we demonstrate several

novel Trojans attacking cache coherence in 2.5D designs. We

illustrate the risks for these systems and hope to excite the

architecture community to address these risks. Though we

focus on 2.5D integrated systems, note that these attacks also

apply to general cache-coherent systems integrating closed-

source or hard IP blocks from various vendors.

Hardware Trojans, or Trojans for short [3], are a threat in

which an attacker inﬁltrates some level of the design or fab-

rication process to insert malicious circuitry into a design.

Trojans can cause disastrous system failures via conﬁdential-

ity, integrity, and/or availability violations. Prior work has

shown that Trojans can leak data from memory [4], disrupt

cryptographic security features [5], and induce denial-of-

service attacks [6]. As industry moves towards 2.5D designs

integrating multiple vendor chiplets, speciﬁc chiplets used

in building these systems may be untrustworthy. Even if the

IP vendor is trustworthy, the manufacturing process may

not be, leading to inﬁltration and the insertion of Trojans.

In 2.5D designs, memory coherence is crucial to allow

each component and chiplet to maintain an up-to-date view

of the system’s memory. We identify this system as an ideal

target for Trojan attacks as coherence mechanisms control

how all components communicate data updates. Existing

coherence schemes do not enforce existing virtual/physical

memory permissions, thus, a Trojan connected to the coher-

G. A. Chacon, C. Williams, and P. V. Gratz are with Texas

A&M University (e-mail: ginochacon@tamu.edu, charlesw2000@tamu.edu,

pgratz@gratz1.com).

J. Knechtel and O. Sinanoglu are with New York University Abu Dhabi (e-

mail: johann@nyu.edu, ozgursin@nyu.edu).

ence scheme can directly manipulate any memory region

in the full system regardless of memory permissions or

physical location. Unlike prior packet-level NoC attacks,

Trojans on cache coherence do not need to be physically

on the path between the victim and the memory controller

to launch effective attacks. Despite this attractiveness, there

is a lack of works deeply exploring coherence exploits and

their defense in 2.5D systems or otherwise.

Here, we propose several new Trojan attacks that lever-

age the coherence system protocol to maliciously manipu-

late the victim process’ memory. We ﬁrst describe a set of

new fundamental attacks that a Trojan can mount on coher-

ence systems, passive reading,masquerading,modifying, and

diverting attacks, according to Basak et al.’s taxonomy [7].

Here we assume an attacker implements these coherence

system attacks in hardware through compromised design or

manufacturing. While each of these attacks individually vi-

olates a system’s security, we further show that adversaries

can orchestrate them together to perform complex Forging

attacks that modify any process’ memory. These purely

hardware attacks cannot be thwarted by contemporary soft-

ware defense mechanisms since all exploited coherence

interactions are transparent to software and legal within the

coherence protocol. Further, no prior work considers such

attacks on coherence systems, neither in the context of 2.5D

systems with chiplets nor traditional 2D systems.

Contributions. This work provides new insights into how

Trojans can manipulate coherence systems to violate the

security of a chiplet system. We present a simulated example

of a substantial attack that can directly manipulate memory

in an address space other than that of the compromised

chiplet. This work makes the following contributions:

•We present potential attack stages available to a

Trojan designers exploiting coherence systems.

•We demonstrate how to use these fundamental

stages to orchestrate a complex Trojan attack in a

chiplet-based system.

•We provide suggestions for future work on harden-

ing modern chiplet designs.

arXiv:2210.00058v1 [cs.CR] 30 Sep 2022

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1HardwareTrojanThreatstoCacheCoherenceinModern2.5DChipletSystemsGinoA.Chacon,CharlesWilliams,JohannKnechtel,OzgurSinanoglu,andPaulV.GratzAbstractAsindustrymovestowardchiplet-baseddesigns,theinsertionofhardwareTrojansposesasignicantthreattothesecurityofthesesystems.Thesesystemsrelyheavilyoncachecoh...

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1 Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems

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