The Champ ionship Simulator Architectural Simulation for Education and Competition Nathan Gober Gino Chacon Lei Wang Paul V . Gratz

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The Championship Simulator: Architectural

Simulation for Education and Competition

Nathan Gober∗, Gino Chacon∗, Lei Wang∗, Paul V. Gratz∗,

Daniel A. Jim´

enez∗, Elvira Teran†, Seth Pugsley‡, Jinchun Kim∗

∗Texas A&M University

{ngober, ginochacon, wilsonwang2019}@tamu.edu, pgratz@gratz1.com, djimenez@acm.org, cienlux@gmail.com

†Texas A&M International University

elviraterangarcia@gmail.com

‡Intel

sethpugsley@gmail.com

Abstract—Recent years have seen a dramatic increase in the

microarchitectural complexity of processors. This increase in

complexity presents a twofold challenge for the ﬁeld of computer

architecture. First, no individual architect can fully comprehend

the complexity of the entire microarchitecture of the core. This

leads to increasingly specialized architects, who treat parts of

the core outside their particular expertise as black boxes. Sec-

ond, with increasing complexity, the ﬁeld becomes decreasingly

accessible to new students of the ﬁeld. When learning core

microarchitecture, new students must ﬁrst learn the big picture of

how the system works in order to understand how the pieces all

ﬁt together. The tools used to study microarchitecture experience

a similar struggle. As with the microarchitectures they simulate,

an increase in complexity reduces accessibility to new users.

In this work, we present ChampSim. ChampSim uses a

modular design and conﬁgurable structure to achieve a low

barrier to entry into the ﬁeld of microarchitecural simulation.

ChampSim has shown itself to be useful in multiple areas of

research, competition, and education. In this way, we seek to

promote access and inclusion despite the increasing complexity

of the ﬁeld of computer architecture.

I. INTRODUCTION

Computer architecture has developed over the decades into a

mature ﬁeld with strong specialization. Processors have grown

in complexity, gaining more and more features as transis-

tor density continues to increase, and as each new iterative

innovation builds upon previous solutions. An increasingly

lengthy historical perspective is required to fully appreciate

the state of the leading edge of processors. Also, the trend

of software tools used to assist microarchitecture development

has been towards large, complex, and monolithic simulation

environments.

Simultaneously, computer architecture education has be-

come a core component of undergraduate computer engineer-

ing and computer science curricula. A basic understanding

of computer architecture topics such as cache replacement

and branch prediction is no longer restricted to graduate

level courses, but can easily ﬁnd a place in an undergraduate

research project or classroom assignment. While precise tools

used by experts provide a high level of correctness, students

need tools appropriate for their level of knowledge, experience,

and ability. A large gap exists between the need for arcane

tools used by experts and the need for accessible tools that

can be used by novices. In this gap should stand a tool that

strikes a balance between correctness and accessibility.

Computer hardware development is impeded by the long

production pipelines required to realize a design. If a hardware

design must traverse its entire life cycle in order to be evalu-

ated, it may take many years to produce a well-tested design. It

is furthermore infeasible to tape out many iterations of a design

in order to evaluate their comparative performance. In order

to reduce costs and mitigate long production pipeline times,

hardware architects turn to higher-level software simulation of

their designs. Simulation bridges the gap by enabling rapid

comparisons between the designs, giving an approximation

of the system’s performance. Software simulation of designs

is, by its nature, far slower than the hardware designs being

evaluated, but allows for a much shorter design-to-evaluation

time.

The advancement of the ﬁeld of computer architecture

depends on accurate and rapid simulation. Simulator authors

make tradeoffs between evaluation time and simulation ac-

curacy. The landscape of simulators today is wide, but few

see broad usage. Some simulators are less concerned with

evaluation time, and are more concerned with simulation

accuracy. Others place greater emphasis on model performance

over a more detail-oriented approach. Such simulators ﬁnd

their balance in a short evaluation time.

In this work, we present ChampSim, a simulator designed to

promote innovative research, inclusive education, and healthy

competition in the ﬁeld of computer architecture. The Champ-

Sim simulator is derived from the simulation tools used in

the Second Data Prefetching Competition, which was held in

conjunction with ISCA 2015. ChampSim simulates a hetero-

geneous multicore system with an arbitrary memory hierarchy,

where each out-of-order core can be conﬁgured arbitrarily. It

is intended to promote access in the rapidly-growing ﬁeld of

computer architecture. To accomplish this, we keep three key

principles in mind: Low startup time, broad applicability, and

design conﬁgurability. These design principles have led to a

arXiv:2210.14324v1 [cs.AR] 25 Oct 2022

simulator that favors usability and rapid iteration.

This paper will discuss in detail the purpose, design, and

effectiveness of the ChampSim simulator, beginning with a

discussion of the guiding principles of the design in Section II,

details on the key features of ChampSim’s modular architec-

ture in Section III, a history of ChampSim’s application in the

ﬁeld and a vision of its continuing place in Section IV, and a

list of future development plans in Section VI.

II. THE CHAMPSIM ARCHITECTURAL SIMULATOR

The ChampSim simulator has its roots in the simulation

environment used for the Second Data Prefetching Competi-

tion [1]. In a competition environment, it is valuable to have an

easy-to-use environment to encourage wide participation and

a variety of novel submissions. These accessibility principles

have continued through the development of ChampSim and

have emerged into three guiding design principles: low startup

time, broad applicability, and high conﬁgurablilty.

A. Low startup time

While failure is an important part of learning, wrangling

with a highly complex simulator before even beginning the

implementation of a new idea can frustrate the learning process

of any student or beginning researcher. With this insight in

mind, we seek that a new user should be able to download

and compile ChampSim in a few minutes, create their ﬁrst

design in a few hours, and perform new and meaningful

computer architecture research within a few weeks. In each

of the applications for which ChampSim is intended, it is

valuable that a user is able to begin using the simulator quickly.

Furthermore, the runtime of the simulation should be short

enough to provide quick feedback for a novice user.

Many general-purpose processors have a lot in common.

Designs are pipelined, usually with a decoupled, in-order front

end and an out-of-order back end. Many researchers are not

seeking to modify these basic design aspects, but have a

particular element of the design in mind that they intend to

study or improve. ChampSim presents a selection of areas

that commonly see research activity as conﬁgurable modules:

branch predictors, cache replacement policies, branch target

buffers, and both instruction and data prefetchers. These

modules provide an intuitive interface into a larger system,

allowing designers to test new designs quickly and effectively,

while affording them the opportunity to not have to worry

about the parts of the system they are not studying.

Reference implementations of legacy modules, such as the

GShare branch predictor [2] or the next-line prefetcher, are

included with the simulator. These reference implementations

can be used as starting points for new designs or as placehold-

ers if the user is not interested in modifying those particular

modules.

B. Broad Applicability

A researcher seeking to perform hardware research should

not be expected to be broadly familiar with a variety of

programming languages or to track their changes over time.

Therefore, for the sake of inclusion, we seek that a user should

only need an entry-level understanding of C++, the language

in which ChampSim is written, to perform research using

ChampSim. The interface to an simulator should be simple

and present the user with a few meaningful choices that map

well onto their experience. Each module is fundamentally only

the implementation of a few functions.

ChampSim is trace-driven, meaning that simulation is per-

formed in two stages. First, the workload to be simulated

is instrumented and run ofﬂine. The tracing instrumentation

produces a digest of the program’s activity, called a trace.

The tracing step can be performed ofﬂine from the simulation

step and the trace can be stored in a repository and made

available to users. To test a simulated design, the user selects

a trace ﬁle as input. The trace is streamed into the program

as a stand-in for actual program execution. This strategy

sacriﬁces a modest amount of accuracy, particularly in how

the operating system interacts with the program, in favor of

ease in reproducing results and of speed of the model. It is

simpler for ChampSim to read a decoded trace ﬁle than to

execute an external program, and given established, compiled

repositories of traces, it is a helpful abstraction to the user to

remove another step of environment setup.

Users are able to generate their own program traces with

the included “tracer” tracing tool, included in the ChampSim

package. The included tracer is built upon Intel PIN [3], a

well-documented tool for instrumenting programs at runtime,

though other tool sets, such as DynamoRIO [4], can be used.

Alternately, instruction traces can be dumped from execution-

driven simulators such as gem5 or QFlex [5]–[7]. The tracer

inspects every instruction the program runs and encapsulates

each instruction into a decoded format that includes the

instruction pointer, branching behavior, and which registers

and memory locations form the input and output operands for

the instruction. The concatenation of many instructions forms

the entire trace. This trace format permits ChampSim to run

with low memory requirements, since the trace does not need

to be held in memory but can be streamed off the disk after

inline decompression.

C. Design conﬁgurability

ChampSim is capable of modeling a large variety of

commodity processors. A conﬁguration ﬁle speciﬁes many

aspects of the modeled CPU core, including frequency, cache

conﬁguration, re-order buffer size, load and store queue sizes,

widths for instruction fetch, decode, execution and retire, and

a variety of latencies for different components. In addition,

ChampSim includes a DRAM system that models bank and

bus contention. The trace format includes only virtual memory

addresses, so ChampSim simulates a page table and TLB

hierarchy with arbitrary mappings of virtual to physical pages.

Each cache must be conﬁgured with a prefetcher (to

simulate no prefetcher, there is an included “do-nothing”

prefetcher) and a replacement policy. The cache interfaces with

a read queue, a write queue, and a prefetch queue. Prefetches

originating from the cache level are placed in its prefetch

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TheChampionshipSimulator:ArchitecturalSimulationforEducationandCompetitionNathanGober,GinoChacon,LeiWang,PaulV.Gratz,DanielA.Jim´enez,ElviraTerany,SethPugsleyz,JinchunKimTexasA&MUniversityfngober,ginochacon,wilsonwang2019g@tamu.edu,pgratz@gratz1.com,djimenez@acm.org,cienlux@gmail.comyTexasA&M...

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The Champ ionship Simulator Architectural Simulation for Education and Competition Nathan Gober Gino Chacon Lei Wang Paul V . Gratz

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