
END-TO-END QOSFOR THE OPEN SOURCE SAFETY-RELEVANT
RISC-V SELENE PLATFORM
Pablo Andreu§, Carles Hernandez§, Tomas Picornell§, Pedro Lopez§, Sergi Alcaide†,‡, Francisco Bas†,‡,
Pedro Benedicte†, Guillem Cabo†, Feng Chang†, Francisco Fuentes†, Jaume Abella†
§Universitat Politecnica de Valencia (UPV), Spain
†Barcelona Supercomputing Center (BSC), Spain
‡Universitat Politecnica de Catalunya (UPC), Spain
ABSTRACT
This paper presents the end-to-end QoS approach to provide performance guarantees followed in the
SELENE platform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time
systems. Our QoS approach includes smart interconnect solutions for buses and NoCs, along with
multicore interference-aware statistics units to, cooperatively, achieve end-to-end QoS.
1 Introduction
Increasing performance demands for safety-related systems impose the adoption of higher-performance multi-processor
systems-on-chip (MPSoCs). However, those MPSoCs include medium or large multicores with cache memories,
accelerators and memory controllers, which need being shared dynamically and at fine-grain (e.g. below microsecond
scale) for efficiency reasons. This clashes against common practice where few hardware resources are shared, and
sharing occurs at a coarse granularity (e.g. above millisecond scale) so that their sharing can be managed at software
level by the hypervisor or the real-time operating system (RTOS).
To address this emerging concern, hardware must provide appropriate support to guarantee performance controllability
so that resources are shared efficiently and
fairly
. In particular, performance concerns such as starvation, deadline
overruns for real-time tasks, and priority inversion must be avoided by construction, and this can only occur if the
MPSoC provides enough Quality-of-Service (QoS) knobs to guarantee a reasonable use of resources to all cores, in line
with user-level requirements.
Some solutions such as resource partitioning (e.g. cache partitioning), and fair and programmable arbitration policies (e.g.
round robin, priority-based) have been explored in the literature to address specific QoS concerns in platforms considered
for safety-related applications. This has been studied, for instance, in the case of the Xilinx Zynq UltraScale+ [
4
], a
platform of interest for avionics industrials among others [
7
]. Unfortunately, in general, those solutions do not provide
easy ways to manage end-to-end QoS so that uncontrolled sharing in a given hardware resource defeats the informed
sharing performed in others.
This paper presents an end-to-end QoS approach to provide performance guarantees, integrated in the SELENE platform,
a high-performance RISC-V based MPSoC for safety-related real-time systems [
2
]. Our QoS approach includes smart
interconnect solutions for buses and NoCs, along with multicore interference-aware statistics units to, cooperatively,
achieve end-to-end QoS, hence enabling software layers with means to guarantee that deadlines are met for real-time
tasks, critical tasks do not experience starvation, and priorities and performance requirements can be met without
priority inversion for mixed-criticality systems.
2 Baseline SoC
The SELENE System-on-Chip (SoC) comprises NOEL-V RISC-V cores and an AI accelerator subsystem. The SELENE
SoC has six 64-bit NOEL-V cores with private L1 data and instruction caches that access to a shared L2 cache using an
AMBA AHB on-chip bus. Cores and accelerators are connected to an AXI network-on-chip (NoC) to access memory
arXiv:2210.04683v1 [cs.AR] 10 Oct 2022